1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a fabricating method of a polycrystalline thin film transistor that is a switching device in a liquid crystal display device.
2. Discussion of the Related Art
In a conventional process for forming a polycrystalline silicon layer, an intrinsic amorphous silicon layer is formed on an insulating substrate by using a plasma chemical vapor deposition (PCVD) method or a low pressure chemical vapor deposition (LPCVD) method. When the amorphous silicon layer has a thickness of about 500 Å (angstroms), it is crystallized into a polycrystalline silicon layer by a crystallization method. The crystallization method is generally either a laser annealing method, a solid phase crystallization (SPC) method or a metal induced crystallization (MIC) method.
In the laser annealing method, an excimer laser beam is applied to an amorphous silicon layer on an insulating substrate to form a polycrystalline silicon layer. In the SPC method, a heat-treatment is applied to an amorphous silicon layer at a high temperature for a time period sufficient to form a polycrystalline silicon layer. In the MIC method, a metal layer is deposited on the amorphous silicon layer. The deposited metal layer is used as a crystallization seed in a subsequent heat-treatment to form polycrystalline silicon. In the MIC method, a large-sized glass substrate may be used as the insulating substrate since the heat-treatment in the MIC method is below 600° C.
The laser annealing method has recently become a more prevalent method in forming a polycrystalline silicon layer. The laser annealing method includes forming an amorphous silicon layer on an insulating substrate and then melting the amorphous silicon layer with a laser. Subsequently, the melted amorphous silicon layer is cooled to form a polycrystalline silicon layer.
The SPC method includes forming a buffer layer on a quartz substrate that can withstand temperatures higher than 600° C. (degrees Celsius). The buffer layer prevents contamination from the the quartz substrate. Next, an amorphous silicon layer is deposited on the buffer layer and is heated in a furnace at a high temperature for a long time period to become a polycrystalline silicon layer. However, the heat-treatment of the amorphous silicon layer performed at a high temperature for a long time period can not obtain a desirable polycrystalline silicon phase, since a direction of grain growth is irregular. Thus, a gate insulating layer contacting the polycrystalline silicon layer is also irregularly formed when the irregularly formed polycrystalline silicon layer is used in a thin film transistor (TFT). Accordingly, a breakdown voltage of the gate insulating layer decreases. Further, since the grain size of the polycrystalline silicon layer is not uniform, the carrier mobility of the TFT is lowered. Furthermore, a high-priced quartz substrate should be used to withstand the high temperatures.
The MIC method forms a polycrystalline layer by using a large-sized glass substrate that has a low cost. However, film quality of the polycrystalline silicon layer is not reliable because a possibility that metal residue exists in the polycrystalline silicon layer is high. Accordingly, a field enhanced metal induced crystallization (FE-MIC) method that improves the MIC method is suggested. In the FE-MIC method, after a metal layer is formed on an amorphous silicon layer, a direct current (DC) high voltage is applied to the metal layer to generate heat. Since the metal layer functions as a catalyst, the metal is referred to as a catalyst metal in a MIC method.
FIGS. 1A to 1F are schematic cross-sectional views showing a fabricating process for a related art polycrystalline silicon thin film transistor using amorphous silicon. In this example, a field enhanced metal induced crystallization (FE-MIC) is used as a crystallization process in FIGS. 1A to 1F.
A buffer layer 2 and an amorphous silicon layer 4 are sequentially formed on a substrate 1, as shown in FIG. 1A. The buffer layer 2 prevents alkali materials in the substrate from causing contamination in subsequent processes. After the amorphous silicon layer 4 is formed, a catalyst metal layer 5 is formed on the amorphous silicon layer 4. In other types of crystallization methods, the catalyst metal layer 5 is not necessary.
A voltage and a heat are applied to the amorphous silicon layer 4, as shown in FIG. 1B. Thus, the amorphous silicon layer 4 is crystallized to form a polycrystalline silicon layer.
As shown in FIG. 1C, silicon island 8 of polycrystalline silicon is formed through patterning of the polycrystalline silicon layer.
As shown in FIG. 1D, a gate insulating layer 10 and a gate electrode 12 are then sequentially formed on the silicon island 8. The silicon island 8 is classified into two regions: a first active region 14 of intrinsic silicon and second active regions 16 and 17, as shown in FIG. 1D. The second active regions 16 and 17 are disposed at respective sides of the first active region 14. The gate insulating layer 10 and the gate electrode 12 are formed on the first active region 14 of the silicon island 8. The gate insulating layer 10 and the gate electrode 12 are patterned with the same etching mask to reduce the number of masks. After the gate insulating layer 10 and the gate electrode 12 are formed, the second active regions 16 and 17 is doped with dopant impurities.
The gate electrode 12 functions as an ion stopper preventing ion penetration into the first active region 14. Electric conductivity of the silicon island 8 depends on the kind of dopant impurity ions used in the ion doping process. For example, when dopant impurities or ions from Group III, such as Boron (B) in B2H6, are doped, the corresponding portion of the silicon island 8 functions as a p-type semiconductor. When dopant impurities or ions from Group V, such as Phosphorous (P) in PH3, are doped, the corresponding portion of the silicon island 8 functions as an n-type semiconductor. The kind of dopant impurities or ions are selected according to the intended use of a semiconductor device. After the ion doping process, the dopant impurities in the semiconductor island 8 are activated with an annealing process.
In FIG. 1E, an interlayer insulating layer 18 is formed on an entire surface of the substrate 1. The interlayer insulating layer 18 has first and second contact holes 16a and 17a exposing the second active regions 16 and 17, respectively.
Source and drain electrodes 20 and 22 are formed on the interlayer insulating layer 18, as shown in FIG. 1F. The source and drain electrodes 20 and 22 are connected, respectively, to the second active regions 16 and 17 through the first and second contact holes 16a and 17a, respectively. Next, a passivation layer 26 is formed on the entire surface of the substrate 1. The passivation layer 26 has a third contact hole 22a exposing the drain electrode 22. Next, a pixel electrode 28 is formed on the passivation layer 26. The pixel electrode 28 is connected to the drain electrode 22 through the third contact hole 22a. Thus, a polycrystalline silicon thin film transistor (p-Si TFT) is completed.
During the fabricating method of the related art p-Si TFT, the surface of the polycrystalline silicon film is damaged during the ion doping process. Accordingly, the polycrystalline silicon film is structurally and electrically degraded due to partial amorphization and dopant impurity-induced crystallinity defects. To solve these problems, an activation process that anneals the polycrystalline silicon film in a furnace is performed at a temperature between about 500° C. and about 600° C. prior to the source and drain electrodes being connected. However, the structural and electrical degradation of the polycrystalline silicon film are not sufficiently repaired even after the activation process.